This invention relates to an error display system of a data processing device containing an independent processor unit such as a micro-processor.
Generally, an error display circuit for use in a data processing device is reset by an initializing signal which is generated when a power supply source is turned on. To detect an error various error detecting means have been used including a parity check circuit or a comparator utilizing a hardware, and contradiction check means for comparison and logic by means of a firmware or software. Where occurrence of an error is detected by the error detecting means, such detection will cause an error retry sequence or an error display indicator on the maintenance panel to be turned on to report the occurrence of the error to an operator.
Where another error occurs during an interval between the error detection and display thereof by the error display circuit such error would be overlooked without being displayed. To prevent this it is necessary to always confirm the error of the data processing device by periodic preventive maintenance. More preferably, error confirmation should be automatically made at the time of turning on the source. Such confirmation can be advantageously performed by storing a test program in a read only memory (ROM) thereby executing the test program at the time of turning on the source. However, in a system wherein an independent processor such as a micro-processor is contained in a data processing device, the error which is detected by the independent processor through a program is displayed by the program. Where the processor correctly executes its normal operation and an error at an external circuit is detected there is no contradiction in its processing operation but where there is a single defect in the processor itself the following problem occurs.
More particularly, although the operating states of the processor differ variously due to the location of the defect, such states are generally classified into the following two cases. In one case, only one of the instructions of the processor becomes impossible to execute, while in the other case all functions become impossible to execute. In the latter case, even when the test program of a ROM is executed the error would not be displayed since normal operation is necessary to display the error, thus causing a failure to display the defect of the processor. In other words, in spite of the fact that the processor involves a single defect, the data processing device would be used without correcting the defect because the error display circuit displays only under normal operating condition.